There are many types of electronic test equipment whose operation includes the digital acquisition of a series of analog voltage values. In some cases, such as in real time digital oscillography, an acquisition record is required for a large number of consecutive samples taken in rapid succession. These types of applications generally require a high speed ADC (Analog to Digital Converter), and are typically very expensive to implement. There are other kinds of related applications where a significantly lower cost is desired, which can be achieved if certain performance requirements can be relaxed. These other applications often take advantage of an expected periodicity wherein the signal's previous behavior is repeated, and given enough time a complete description of the signal can be created by sampling different locations within that behavior during successive instances of the behavior. This can remove the need for sustained high speed operation from the ADC. Some digital oscilloscopes operate in this mode. There is yet another variation on this latter mode, where the signal behavior is not required or expected to repeat its exact waveform during the successive instances of sampling at different locations. For example, an EDA (Eye Diagram Analyzer) is more interested in the locations of edges, their rise and fall times and their exerted voltage levels between transitions, rather than in the particular waveform as a voltage history versus time. EDAs often acquire data for large number of signals at the same time (e.g., for all the signals in a wide bus). It is economically impractical to use an expensive data acquisition technique that might be justifiable for two or four channels in a digital oscilloscope for all sixty-four or one hundred twenty-eight channels of an EDA. Accordingly, there have been developed for such applications various ways to lower the cost of the per-channel data acquisition hardware. These techniques often rely on combinations of delay elements and threshold comparators to produce indications that a certain combination of signal parameters was observed. The occurrence (or lack thereof) is noted, the parameters changed, and the process continued.
For example, U.S. patent application Ser. No. 10/629,269 entitled IMPROVED EYE DIAGRAM ANALYZER CORRECTLY SAMPLES LOW dv/dt VOLTAGES filed 29 Jul. 2003 by David D. Eskeldson and Richard A. Nygaard JR. describes various arrangements of adjustable delay elements and adjustable threshold detectors that indicate, relative to a reference point in time (such as the edge of a clock signal), if a signal of interest within an SUT (System Under Test) exhibited different relationships to the thresholds at closely spaced points in time that are ΔT apart. If it did not, then that negative piece of information (in isolation, anyway) does not tell us much about where the signal was, but if there WERE different relationships exhibited, then we know within certain time and voltage resolutions that the signal was within or passed through a region described by the thresholds and the delays involved. Such detection is termed a “HIT.” It is customary for an ordinate or vertical dimension to represent voltage, while an abscissa or horizontal dimension represents time. In the case of an EDA built around these types of detectors, the region is left to dwell for a certain length of time, the number of HITs recorded in a data structure whose locations correspond to values along the time and voltage axes, and then the region is moved to an adjacent or other selected location in the (time, voltage) plane. The moving of the region can be accomplished through either sweeping the data channel delay or sweeping the clock channel delay. In due course there is enough information amassed to construct an eye diagram from the numbers of HITs recorded in the various locations of the data structure. The eye diagram is depicted as a graph drawn in the (time, voltage) plane.
The prior art (time, voltage) detection mechanisms described in IMPROVED EYE DIAGRAM ANALYZER CORRECTLY SAMPLES LOW dv/dt VOLTAGES are of interest as a point of departure. We now indulge in an extremely abbreviated discussion of those techniques.
Refer now to FIG. 1, wherein is shown a simplified block diagram 11 for a swept data channel delay (time, voltage) detection technique usable in an EDA. FIG. 2 is a simplified block diagram 12 of a similar swept clock channel delay technique. It will be noted that they both use the same mechanism to sample data channel voltage. Wit reference to diagram 47, we could say that the signal of interest must have crossed a horizontal line segment (A to B) at the voltage of the threshold and whose length is the time difference ΔT (we also keep track of where ΔT starts).
In particular, note that in FIG. 1 a variable SWEPT DATA SIGNAL DELAY 10 produces a voltage-compared data channel signal 2 that has been delayed by a variable amount according to what amount of delay in a cycle of swept amounts of delay is currently in effect. The signal 2 is applied to a D input of a latch 3 (A) that is clocked by a clock signal 1, that while it has been delayed by a CONFIGURABLE CLOCK TRIM DELAY mechanism 9, may be thought of as being “the SUT clock”. The voltage-compared data channel signal 2 is also applied to the D input of another latch 4 (B) that is clocked by a slightly delayed (by dt DELAY) version of the clock signal 1. The idea is that if the SUT data signal for that channel passed through the comparison threshold at a time corresponding to the current SWEPT DATA SIGNAL DELAY, then the two latches 3 and 4 will capture different values, which condition is detected by XOR gate 6 and used to increment a # OF HITS COUNTER 7. We call this mechanism a TRANSITION DETECTOR (8), and say that a HIT occurs when the SUT data signal crosses the voltage described by the horizontal line segment A to B (during ΔT).
In FIG. 2 there is a block diagram 12 of the swept clock channel delay technique, which, it will be appreciated from the figure, has the same TRANSITION DETECTOR (8). In fact, the block diagrams 11 and 12 are seemingly identical, although they operate in different manners. What used to be a CLOCK TRIM DELAY 9 in FIG. 1 is now operated as SWEPT CLOCK DELAY 13 in FIG. 2, and what used to be SWEPT DATA SIGNAL DELAY 10 in FIG. 1 is now operated as DATA SIGNAL DE_SKEW DELAY 14.
With both of the techniques of FIGS. 1 and 2 the reliance on detecting a transition through a certain threshold to decide upon a signal value at the time of sampling remains open to failure to detect a HIT when the signal voltage does not aggressively transition at the time of the sample. The basic voltage sampling mechanism relies somewhat on noise in the signal and uncertainty in the comparator to cause HITs along the top (exerted/not exerted) and baseline (not exerted/exerted) signal values. A perfectly clean noise-free signal having no dv/dt between its rise and fall, combined with an ideal comparator, would produce no HITs except during the rise and fall. So we have a situation where, if the SUT's signals are really quite good and the measurement hardware is also really quite good, then the eye diagram goes away except at the transitions; it would seem that better is worse! So far, nobody's equipment is quite that good, but the notion of “better is worse” is a disgusting situation that motivates the improvements described in connection with FIGS. 3 and 4.
Refer now to FIG. 3, wherein is shown a simplified block diagram 16 of an improvement to the above-described TRANSITION DETECTOR 8 that tolerates low dv/dt. It involves the use of a second threshold comparison, and produces a result that could be described as the OR of crossing the above-described horizontal line segment (A to B) with the condition that the signal fell within or crossed a vertical line segment (A to C) located a one end of the horizontal line segment. These line segments are depicted in the diagram 48. In FIG. 3 the architecture shown is for swept data channel delay.
A conditioned SUT data channel signal 17 is applied to a COMPARATOR 19 that also receives a DATA THRESHOLD voltage 20. The logical output signal from the COMPARATOR 19 is applied through an adjustable DELAY 23 (the SWEPT part of this architecture arises from varying the adjustable delay) to the D inputs of LATCHES 27 (A) and 35 (B). (It will be appreciated that the various adjustable delay elements shown can be tapped sequences of buffers in series.)
A conditioned SUT CLOCK IN signal 29 is applied to another COMPARATOR 30 that receives a CLOCK THRESHOLD voltage 31. The logical output of the COMPARATOR 30 is applied through a CLOCK TRIM DELAY 32 (that is typically set and then left alone) as a clocking signal 33 to the LATCH 27, and via an additional DELAY 34 to LATCH 35. DELAY 34 corresponds to the dt DELAY 5 of FIGS. 1 and 2, and the two LATCHES 27 and 35 of FIG. 3 to LATCHES 3 and 4, respectively (for either of FIGS. 1 and 2). XOR gate 38 of FIG. 3 serves the same purpose as XOR gate 6 of FIGS. 1 and 2, and to this point we have described much of the same basic structure as the TRANSITION DETECTOR 8 of FIGS. 1 and 2. That is, if the DATA IN signal 17 experiences a transition through the threshold 20 during a period of time occupied by DELAY 34, as located by DELAY 23, then the two latches 27 and 35 will have different values, and the exerted output from XOR gate 38 will pass through OR gate 39 to set LATCH 40 and produce a signal HIT 41 that is then used in various ways by the balance of the EDA, and that do not concern us here.
Now note that the DATA IN signal 17 is also applied to a second COMPARATOR 18 whose threshold 22 is different from the DATA THRESHOLD 20 by an amount set by an OFFSET VOLTAGE 21. The logical output from COMPARATOR 18 is applied through DELAY 24 (which preferably tracks DELAY 23, save that it may be offset to compensate channel-to-channel skew) as signal 26 to the D input of LATCH 28 (C) that is clocked by signal 33. A moment's consideration will confirm that if the DATA IN signal 17 is, at the time located by the DELAY 32 (i.e., clocked by signal 33), of a value that is within the (signed) OFFSET VOLTAGE 21 from the DATA THRESHOLD 20, then the two LATCHES 28 and 27 will have different values after being clocked by signal 33. As a particular example when the OFFSET value 21 is positive, LATCH 27 will be set, and LATCH 28 will not be set. The underlying implication that may be drawn is that the level (voltage value at the time of sampling) of the SUT data signal of interest is close (within the OFFSET value 21) to the value of the DATA THRESHOLD 20. On the other hand, if the SUT data signal level is safely on one side of the DATA THRESHOLD 20 by an amount exceeding the OFFSET 21, then both LATCHES 27 and 28 will be set, while in the other case (voltage level on the “other side”) neither LATCH will be set. In either case, they (27, 28) are both the same after being clocked by signal 33. However, as noted, in the case of interest (which is a HIT), the LATCHES will be different, and XOR gate 37 will detect such and OR gate 39 will merge this HIT indication with the output of XOR gate 38. The merged result is applied to LATCH 40, from whence things proceed as usual, save that we are now able to detect HITs that may have eluded the TRANSITION DETECTOR 8 of FIGS. 1 and 2. We call this improved mechanism a TRANSITION/RANGE DETECTOR, and say that it detects a HIT when either the SUT data signal crosses the voltage described by the horizontal line segment A to B (during ΔT), or when the SUT signal lies within the voltage range A to C at the start of ΔT, or perhaps (and which is equivalent, but requires slightly different circuitry) lies within the voltage range B to C at the end of ΔT.
Lastly, note optional DELAY 36. If there were no such DELAY 36 then the LATCH 40 captures the results for a cycle of CLOCK IN 31 that is one cycle advanced ahead of the present cycle. In a pipelined system this is not a major shortcoming, as things are later aligned by pipeline delays, anyway. If the delay is present, and chosen to be more than DELAY 34 and less than a clock cycle, then “newest” results are clocked into LATCH 41.
A brief reference to FIG. 4 will reveal a simplified block diagram 45 that is as similar to the block diagram 16 of FIG. 3 as FIG. 2 is similar to FIG. 1. The operation of the circuit is essentially the same as described for FIG. 3, save that the DELAYs 43 and 44 produce a TRIM DELAY that de-skews the data channels, and DELAY 42 operates as a SWEPT CLOCK DELAY.
It is not so much that the above-described systems do not work—they do. But we can imagine other circumstances where we would like more than a simple “it was present” or “it was absent” type of indication for our efforts. For example: “Did it pass all the way through the region, and if so, in which direction?” We might even prefer that the region involved be something other than a line segment or two line segments. But on the other hand, we are mindful that however we choose to augment the acquisition circuitry, we are bound to do it for all sixty-four or one hundred twenty-eight channels, which is a powerful incentive in favor of techniques that return significant amounts of information for relatively little additional hardware. What to do?